MM FPUX: High-performance floating point unit with extended precision arithmetic and special functions

The MM FPUX is a high-performance, low latency, floating point unit IP core supporting multiple precisions with a small gate count of 300K.  It currently supports 32-bit single-precision and 64-bit double-precision arithmetic with a raw 64-bit data path and provision for design upgrade path for migration to support up to 128-bit extended precision.  Clock speeds supported are 50-200 MHz on FPGA and 800 MHz and above for ASIC @ 45nm.

Partially compliant with the IEEE 754-2008 standard, the MM FPUX delivers double-precision compare in 1 cycle, addition/subtraction in 4 cycles, multiplication in 7 cycles, and division in 21 cycles, using a mere 117 mW of power.

Efficient special functions support is available for square root, exponential and natural logarithm, and trigonometric functions.

The attached datasheet provides more information.

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